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| dc.date | 2018-09-01 | |
| dc.date.accessioned | 2018-06-21T17:00:15Z | |
| dc.date.available | 2018-06-21T17:00:15Z | |
| dc.identifier | IAS0150 | en_US |
| dc.identifier.uri | https://dspace.ttu.ee/xmlui/handle/123456789/21 | |
| dc.description | Digital systems, the main design phases. Transformation, optimization and implementation of multi-output logic functions. Systems with memory, control and operation automata, their transformation, optimization and implementation. Design and optimization of digital systems architectures. Overview about basics of digital systems modeling. Introduction to hardware description language VHDL, using it to model digital systems. | en_US |
| dc.language.iso | other | en_US |
| dc.publisher | Department of Computer Systems | en_US |
| dc.rights | Tallinn University of Technology | en_US |
| dc.subject | Hardware | en_US |
| dc.title | Digital Systems | en_US |
| dc.type | Talk/Lecture | en_US |
| compass.learningOpportunitySpecification.assessment | Hands-on exercises and witten exam | en_US |
| compass.learningOpportunitySpecification.level | EQF Level 6::Bachelor | en_US |
| compass.learningOpportunitySpecification.objective | CE-DIG Digital Design | en_US |
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